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RFIC design doesn’t have to be this complicated. With others’ patchwork flows, you have to cross your fingers that your layout will match the schematic specs. If not, you could be heading back to square one. With Analog Office, you can work seamlessly between schematic and layout, verifying performance along the way and uncovering manual errors. It shortens design cycle time and yields RFICs that are right the first time—with less stress. Sound simple? Grab a test copy at www.awrcorp.com/AO.

Siemens

Siemens IT Solutions and Services PSE Achieves First Time Silicon Success Using Analog Office.

The Design Challenge

Siemens IT Solutions and Services PSE was faced with the challenge of designing several ultra-low-power, high-frequency receiver front-ends at 2.4 GHz, and 5.8 GHz for an embedded radio application. The team, which had previously used AWR’s Microwave Office® design suite, and Visual System Simulator™ product, needed a similar and efficient design approach for its RFIC work.

The requirements were extremely exacting: to deploy an intuitive, easy-to-use, RF-centric design environment that would support critical RF blocks with little digital content. It was important to provide tight integration with the system simulation and electromagnetic (EM) tools, as well as robust frequency- and time-domain solvers, including productive layout and extraction capabilities. An open system was essential in order to integrate in-house physical verification tools. The software had to be capable of designing an RF chain from the antenna to the baseband, and from the system-level design down to layout in a single environment.

The preference was to use a PC-based design platform that would enable designers to easily interchange design files and use a flexible work schedule to support the existing RF system-centric workflow. In addition to design capabilities, it was necessary for the software to support silicon RF and silicon germanium (SiGe) foundry kits and to provide porting of foundry PDKs into the Analog Office environment.

The Solution

The AWR Analog Office RFIC design environment was a perfect fit for what the Siemens team was looking for in an EDA tool suite. The first step was to port the existing foundry PDK into the AWR environment. The AWR support team worked jointly with the Siemens team to create and validate the electrical kit through automated wizards generating the symbols, schematics, and process models for the Analog Office tool.

The parameterized cells (PCells) were later derived by the Siemens team by interfacing the legacy, foundry-provided PCell generator, thus ensuring correct-by-design PCell compatibility.

The Analog Office software enabled the Siemens team to quickly complete their circuit simulations, both transient-domain using HSPICE® and frequency-domain using AWR simulators. The tuning features enabled faster design of the critical circuit blocks, and different optimization algorithms were used in the Analog Office software to derive optimum performance with lowest noise.

The unique AWR Unified Data Model™, which supports electrical and physical co-design in one environment, enabled the Siemens team to interactively create the layout for the corresponding circuit. The unified data model enabled the Siemens team to perform RCLK parasitic extraction and simulation on a subset of the layout and routed blocks without having to wait for complete physical implementation.

The system- and circuit-driven design methodology provided an accurate representation of the layout and assured RF convergence, as the schematic and layout represented the same data and parasitic models. The final chip was validated for tape-out using the foundry-specified legacy sign-off tool, and experimentally using a Siemens internally-developed proprietary verification engine that was interfaced by the Siemens team to Analog Office through AWR’s open design environment.

Because Analog Office software provides the same intuitive environment as the Microwave Office design style, the Siemens designers were productive from the start, cutting weeks of ramp-up time out of the overall design flow. Once the PDK porting efforts were finished, the AWR RFIC design flow in the Analog Office design suite enabled the Siemens team to tape out ahead of schedule, observe close correlation between measured and simulation results, and achieve first-time silicon success for the multiple chip design project.

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BAE Systems

Analog Office Software and PDK Support BAE System’s Revolutionary Mixed-signal Photonics Chip Design.

Project Background

BAE Systems, in partnership with AWR, MIT, Cornell University, and Alcatel-Lucent Bell Labs, has been working to produce a new breed of devices that embed photonic devices into silicon-based integrated circuits (ICs), enabling computer chips to perform digital, radio frequency, and photonic functions in a single chip. The Electronic and Photonic Integrated Circuits (EPIC) program, which is funded by Defense Advanced Research Projects Agency (DARPA), intends to produce a viable mixed-signal electronic/photonic application in less than five years. This research is being built on by Alcatel-Lucent Bell Labs, which recently demonstrated the first CMOS silicon-based tunable optical waveguide equalizer, a major step in the industry’s drive toward sophisticated, high-density, low-cost silicon chip-based optical networking devices.

The Design Challenge

BAE Systems is taking a mature electronics process in complementary metal oxide semiconductor (CMOS) and adapting it to add complex photonics functions ranging from the photonic processing of massive amounts of RF bandwidth to extremely high-speed digital interconnects. The team has developed a wide range of monolithically integrated CMOS-compatible photonic devices including ultra-low-power-consumption silicon ring optical modulators, fourth-order narrowband optical filters with tunable passbands and center wavelengths, and silicon-germanium (SiGe) waveguide photodetectors. The design of these revolutionary mixed-signal chips is extremely complex, and accurate behavioral models are key to developing and producing high quality performance at a reasonable cost.

The Solution

BAE Systems uses Analog Office design suite to develop RF and microwave photonic applications, and AWR provides consulting services for the development of models and process design kits (PDKs). AWR has been working closely with photonics designers at BAE Systems and Bell Labs to develop accurate behavioral models based on the EPIC data. The two teams are also working together to create a PDK that will enable accelerated silicon tapeout of the photonics chips. In addition, AWR’s Analog Office software is being used to extract the models.

The integrity of the electrical and physical model data is often an issue between foundry customers, foundries, and EDA vendors. As part of its commitment to high-level customer service, AWR has invested considerable research and development in PDKs for its Analog Office design suite software. The PDKs are customized for the unique AWR open design platform with its unified data model, and carefully developed from supplied technology files, device models, and design rules specifically for Analog Office. AWR PDKs are subjected to an extensive level of validation at both cell and circuit level to ensure quality and conformance to best-in-class design methodologies for high-frequency RFIC designs.

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Epic Communications, Inc.

Leveraging its Design Experience and Success with Microwave Office, Epic Communications Designs Customized RFIC Transceivers with Analog Office in Record Time.

The Design Challenge

Epic Communications (Epicom) has embarked on the design of a customized transceiver using a silicon germanium (SiGe) bipolar complimentary metal oxide semiconductor (BiCMOS) process. Initially, the integrated circuit (IC) implementation includes development of a transmitter, receiver, and a synthesizer including a voltage-controlled oscillator (VCO) and phase-locked loop (PLL).

The Epicom design team combines strengths in wireless system architecture and active device design, as well as passive RF components. The team had already used Microwave Office® software for the design of numerous monolithic microwave IC (MMIC) products, such as low-noise amplifiers (LNAs), power amplifiers (PAs), and integrated passive devices (IPDs), with both active and passive circuits on a single die. The designers were comfortable incorporating Analog Office into their design flow as the tool of choice for their RFIC transceiver.

Epicom recognized the need for an easy-to-use and intuitive environment similar to Microwave Office for the design of the RF transceiver silicon. The environment was required to support the integration of existing intellectual property (IP) blocks implemented in formats from different tool vendors. Epicom designers wanted a complete design suite covering design entry and physical layout, time- and frequency-domain circuit simulation capabilities, a tighter link between the electrical and physical circuitry, a platform for integration of existing IP blocks, and an interface for a foundry-supported physical verification engine. The tape-out schedule was tight, with limited resources dedicated to the project. In addition to design work, the circuit designer was responsible for the layout implementation, so limited design iteration and first-time RF convergence was extremely crucial.

The Solution

The AWR Analog Office solution provided a complete and comprehensive environment for Epicom designers to develop the RFIC transceiver. The ability to utilize previous designs in the Analog Office environment, including layout and test benches, was a big plus. The software enabled the Epicom team to tapeout the design on schedule, providing full-chip layout integration and verification, including design rule check (DRC) and layout vs. schematic (LVS) checks to the foundry-supported decks.

The entire design cycle from architecture definition to silicon tape-out was approximately three months. Due to prior experience with the capabilities offered in AWR’s Microwave Office design suite, the Epicom design team had virtually no ramp-up time and no need to learn the intricacies of a new tool. The ability to use the same environment for both GaAs and silicon designs, combined with Analog Office advanced silicon layout capabilities, enabled the designers to focus on the design issues rather than spending time on tool support.

The unified data model common between electrical and physical circuits enabled the designers to complete their layout and meet specifications quickly, without spending valuable time on endless iterations to meet tighter design requirements.

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